In the electric industry, memory devices are of vital application in various kinds of computer, communication, and consumer electronic products. In the electric equipment, memory devices are employed for the storage and exchange of operating data and information. The information can be stored temporarily or permanently in various kinds of memory devices, depending on the system design and needs. The DRAM is one of the most important memory devices for providing temporary data storage in numerous system applications. In the last decade, the DRAM is the flagship product of the semiconductor industry for its high-density structure and wide applications.
In general, a DRAM cell is composed of a transistor and a capacitor. A MOSFET (metal oxide semiconductor field effect transistor) is utilized preferably to enable the writing and the reading of the data. The capacitor is employed to store electric charge, wherein the data is represent by the voltage level of the electric charge. The DRAM cells can be accessed with unlimited reading and writing cycles with high frequency and reliability.
For reducing the cost and increasing the competitive power of the DRAM devices, the density of DRAM cells on unit chip area must be raised continuously. The number of DRAM cells on each chip has increased from 16M to 64M and it is believed that the 256M and higher volume DRAM chips will become the most competitive products before the end of the twentieth century. With the fast increasing density, the area occupied by each DRAM cell with a transistor and a capacitor has to narrow down several times while providing the same function and operation on data storage and exchange.
However, since the storage capacity of a capacitor is proportional to the surface area of the electrode, the capacitor structure of the traditional plate electrode must be improved. The capacitor structure must be redesigned to provide raised storage capacity or the capacitance under per unit chip area. In prior art designs, various type of stacked-capacitor structure had been proposed. As an example, M. Sakao et al. proposed a capacitor-over-bit-line (COB) cell structure in their work "A Capacitor-Over-Bit-Line (COB) Cell with a Hemispherical-Grain Storage Node for 64 Mb DRAMs" (in IEDM Tech. Dig., p. 655, 1990).
In the work of M. Sakao et al., it is disclosed that three-dimensional memory cells, such as stacked or trench capacitor cells, are necessary for future DRAMs in order to obtain sufficient storage capacitance in a small area. Several stacked capacitor cells have been proposed for 64 Mb DRAMs, because, as compared to trench capacitor cells, their fabrication procedure is relatively simple and they offer higher immunity to soft error. In the stacked capacitor cell, large capacitance can be obtained by increasing storage node height, but this causes difficulties with optical delineation and patterning. Three dimensionally arranged storage node structures have been proposed. However, their attempts cause difficulties of fabrication procedure.
H. Wantanabe et al. disclosed a new cylindrical capacitor structure in their work "A New Cylindrical Capacitor Using Hemispherical Grained Si (HSG-Si) for 256 Mb DRAMs" (in IEDM Tech. Dig., p. 259, 1992). A new selective etching technique using a low-pressure vapor hydrogen fluoride is developed to form the cylindrical capacitor electrode. A high selective etching (2000 times) of borophospho-silicate-glass to SiO.sub.2 is realized with the technique. Disilane molecule irradiation in ultra-high vacuum chamber achieves the HSG-Si formation on the whole surface of phosphorous doped amorphous Si cylindrical electrode.
However, conventional stacked-capacitor structures have some unsolved strength problem in the fabrication of three-dimensional electrodes. In general, most of the three dimensional electrode structure are composed of several silicon layer which are deposited and defined separately. The three-dimensional structures with interfaces of several deposition processes on a single node are found to suffer from defect issues like cracks. The problem greatly damages the yield of the process. In addition, for developing future high density DRAMs, the conventional stacked-capacitor structure can not get sufficient capacitance. What is needed in the field is an improved design of a capacitor cell structure with raised storage capacitance without strength problem like crack issue during manufacturing processes.